Fellowship - Signal processing/CMOS integrated circuit technologies for ultra-compact 3D depth-imaging systems
Japan

Job Reference: 00079

Location: Japan

Closing Date: 06/12/2019

Job Posted Date: 30/08/2019

Salary: C10M JPY

Employment Type: Toshiba Fellowship

Business Type: Research & Development

Signal processing/CMOS integrated circuit technologies for ultra-compact 3D depth-imaging systems

Background
There is a strong demand to reduce both the cost and size of 3D depth-imaging systems, including LiDAR, for use in ADAS, drone, and precise-motion robotics applications.
We are seeking a Fellow with an innovative idea and the passion to realise the potential of long-range solid-sate LiDAR.

Description of Research
The aim of this programme is to demonstrate the proposed idea through optimized design, implementation and evaluation of the system by using the design-to-production flow of TOSHIBA original photonic-device-mixed CMOS and MEMS processes.

Required Knowledge and Skills
Candidates should possess expertise in (1) signal processing or (2) integrated circuit design for imaging system (ex. CMOS image sensor, ToF camera, certain depth sensor).
More specifically,                                                                                              
(1) RTL design, system design and evaluation using FPGA, MATLAB, C, and python  
(2) CMOS integrated (Mixed-Signal) circuit design, andexperience of Cadence Tools.

Related papers
[1] K. Yoshioka, A. Sai, et al, “A 20ch TDC/ADC hybrid SoC for 240× 96-pixel 10%-reflection< 0.125%-precision 200m-range imaging LiDAR with smart accumulation technique,” ISSCC Digest Technical Papers, p.92-93, Feb. 2018.                                                
[2] A. Sai, et al., “A 5.5mW ADPLL-based receiver with hybrid-loop interference rejection for BLE application in 65nm CMOS,” IEEE Journal of Solid-State CircuitS, Vol.51, No.12, pp. 3125-3136, Dec. 2016.                                                                              
[3] A. Sai, et al., “A 65nm CMOS ADPLL with 360μW 1.6ps-INL SS-ADC-Based Period-Detection-Free TDC,” ISSCC Digest Technical Papers, pp. 336-337, Feb. 2016.                                                                                                            
[4] H. Okuni, A. Sai et al., “A 5.5mW ADPLL-based receiver with hybrid-loop interference rejection for BLE application in 65nm CMOS,” ISSCC Digest Technical Papers, pp. 436-437, Feb. 2016.                                                                                                                       
[5] A. Sai, et al, "A Digitally Stabilized Type-III PLL Using Ring VCO with 1.01psrms Integrated Jitter in 65nm CMOS," ISSCC Digest Technical Papers, pp.248-250, Feb. 2012.                                                                                                                                                                                                                                        
[6] A. Sai, et al, "A 570fsrms Integrated-Jitter Ring-VCO-Based 1.21GHz PLL with Hybrid Loop," ISSCC Digest Technical Papers, pp.98-100, Feb. 2011.             
 

 

 

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